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1 ? fn4749.3 HIP6501A triple linear power controller with acpi control interface the HIP6501A, paired with either the hip6020 or hip6021, simplifies the implementation of acpi-compliant designs in microprocessor and comput er applications. the ic integrates two linear controllers and a low-current pass transistor, as well as the monitoring and control functions into a 16-pin soic package. on e linear controller generates the 3.3v dual voltage plane from an atx power supply?s 5vsb output during sleep states (s3, s4/s5), powering the pci slots through an external pass transistor, as instructed by the status of the 3.3v dual enable pin. an additional pass transistor is used to switch in the atx 3.3v output for pci operation during s0 and s1 (active) operatingstates. the second linear controller supp lies the computer system?s 2.5v/3.3v memory power through an external pass transistor in active states. during s3 state, an integrated pass transistor supplies the 2.5v/3.3v sleep-state power. a third controller powers up a 5v dual plane by switching in the atx 5v output in active states, or the atx 5vsb in sleep states. the HIP6501A?s operating mode (active-state outputs or sleep-state outputs) is selectable through two control pins: s3 and s5 . further control of the logic governing activation of different power modes is offered through two enabling pins: en3vdl and en5vdl. in active states, the 3.3v dual linear regulator uses an ex ternal n-channel pass mosfet to connect the output (v out1 ) directly to the 3.3v input supplied by an atx (or equivalent) power supply, while incurring minimal losses. in sleep state, the 3.3v dual output is supplied from the atx 5vsb through an npn transistor, also external to the controller. active state power delivery for the 2.5/3.3v mem output is done through an external npn transistor, or an nmos switch fo r the 3.3v setting. in sleep states, conduction on this output is transferred to an internal pass transistor. the 5v dual output is powered through two external mos transistors. in sleep states, a pmos (or pnp) transistor conducts the current from the atx 5vsb output, while in active states, current flow is transferred to an nmos transistor connected to the atx 5v output. similar to the 3.3v dual output, the operation of the 5v dual output is dictated not only by the status of the s3 and s5 pins, but that of the en5vdl pin as well. features ? provides 3 acpi-controlled voltages - 5v active/sleep (5v dual ) - 3.3v active/sleep (3.3v dual ) - 2.5v/3.3v active/sleep (2.5v mem ) ? simple control design - no compensation required ? excellent output voltage regulation -3.3v dual output: 2.0% over temperature; sleep states only - 2.5v/3.3v output: 2.0% over temperature; both operational states (3.3v setting in sleep only) ? fixed output voltages require no precision external resistors ? small size - small external component count ? selectable 2.5v mem output voltage via fault/msel pin - 2.5v for rdram memory - 3.3v for sdram memory ? under-voltage monitoring of all outputs with centralized fault reporting ? adjustable soft-start function eliminates 5vsb perturbations pinout HIP6501A (soic) top view ordering information part number temp. range (c) package pkg. dwg. # HIP6501Acb 0 to 70 16 ld soic m16.15 hip6501eval1 evaluation board 10 11 12 13 14 15 16 7 6 5 4 3 2 1 en3vdl 3v3dlsb s3 3v3dl en5vdl 5vsb vsen2 12v dla ss fault/msel 5vdl s5 drv2 gnd 5vdlsb 9 8 data sheet january 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 block diagram s3 5vsb gnd 4.5v/4.0v ea2 5vsb por s5 12v 5vdlsb + - 3v3dl fault/msel uv detector to uv detector to 12v 12v bias en5vdl 5vdl ea4 3v3dlsb ss uv comparator 3.75v dla vsen2 drv2 en3vdl 40 a 0.2v monitor and control 10.8v/9.0v 12v monitor 1.265v mem voltage select comp temperature monitor (tmon) 10 a delay + - + - + - + - + - - + figure 1. HIP6501A
3 simplified power system diagram typical application +5v sb q3 2.5v mem linear HIP6501A +3.3v in +12v in s5 en5vdl +5v in 3.3v dual 5v dual control q1 q4 q5 q2 linear fault s3 en3vdl shutdown controller logic controller figure 2. gnd 5vsb +3.3v in +5v sb vsen2 drv2 s3 c out2 HIP6501A 12v +12v in v out2 2.5/3.3v mem q1 slp_s3 slp_s5 s5 v out1 3.3v dual c out1 +5v in c out3 v out3 5v dual 3v3dl 3v3dlsb q2 q3 q4 q5 dla 5vdlsb fault/msel 5vdl ss en5vdl en5vdl en3vdl en3vdl r sel shutdown fault figure 3. c ss HIP6501A
4 absolute maximum rati ngs thermal information supply voltage, v 5vsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v 12v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +14.5v dla, drv2 . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v to v 12v +0.3v all other pins . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v to 5vsb + 0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 3 [5kv] recommended operating conditions supply voltage, v 5vsb . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% secondary bias voltage, v 12v . . . . . . . . . . . . . . . . . . . . +12v 10% digital inputs, v s3 , v s5 , v en3vdl , v en5vdl . . . . . . . . . .0 to +5.5v ambient temperature range . . . . . . . . . . . . . . . . . . . . . 0c to 70c junction temperature range. . . . . . . . . . . . . . . . . . . . 0c to 125c thermal resistance (typical, note 1) ja (c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications recommended operating conditions, unless otherwise noted. refer to figures 1, 2 and 3 parameter symbol test conditions min typ max units vcc supply current operating supply current i 5vsb -20- ma shutdown supply current i 5vsb(off) v ss = 0.8v, s3 = 0, s5 = 0 - 10 - ma power-on reset, soft-start, and 12v monitor rising 5vsb por threshold --4.5v 5vsb por hysteresis -0.2- v rising 12v threshold - - 10.8 v soft-start current -10- a shutdown soft-start voltage --0.8v 2.5v/3.3v linear regulator (v out2 ) regulation --2.0% vsen2 nominal voltage level v vsen2 r sel = 1k ? -2.5- v vsen2 nominal voltage level v vsen2 r sel = 10k ? -3.3- v vsen2 under-voltage rising threshold -75- % vsen2 under-voltage hysteresis -6- % vsen2 output current i vsen2 5vsb = 5v 250 300 - ma drv2 output drive current i drv2 5vsb = 5v, r sel = 1k ? 20 30 - ma drv2 output impedance r sel = 10k ? - 200 - ? 3.3vdual linear regulator (v out1 ) sleep-mode regulation --2.0% 3v3dl nominal voltage level v 3v3dl -3.3- v 3v3dl under-voltage rising threshold - 2.450 - v 3v3dl under-voltage hysteresis - 200 - mv 3v3dlsb output drive current i 3v3dlsb 5vsb = 5v 5.0 8.5 - ma dla output impedance -90- ? HIP6501A
5 functional pin description 5vsb (pin 1) provide a 5v bias supply for the ic to this pin by connecting it to the atx 5vsb output. this pin also provides the base bias current for all the external npn transistors controlled by the ic. the voltage at this pin is monitored for power-on reset (por) purposes. gnd (pin 8) signal ground for the ic. all voltage levels are measured with respect to this pin. s3 and s5 (pins 6 and 7) these pins switch the ic?s oper ating state from active (s0, s1) to s3 and s4/s5 sleep states. connect s3 to slp_s3 and s5 to slp_s5 . these are digital inputs featuring internal 70k ? (typical) resistor pull-ups to 5vsb. internal circuitry de- glitches the s3 pin for disturbances. additional circuitry blocks any illegal state transitions (such as s3 to s4/s5 or vice versa). when entering an s4/s5 sleep state, the s3 signal is allowed to go low as far as 200 s (typically) ahead of the s5 signal. en3vdl and en5vdl (pins 2 and 5) these pins control the logic governing the output behavior in response to s3 and s4/s5 requests. these are digital inputs whose status can only be ch anged during active states operation or during chip shutdown (ss pin grounded by external open-drain device). the input information is latched-in when entering a sleep state, as well as following 5vsb por release or exit from shutdown. fault/msel (pin 9) this is a multiplexed function pin allowing the setting of the memory output voltage to either 2.5v or 3.3v (for rdram or sdram memory systems). the memory voltage setting is latched-in 3ms (typically) afte r 5vsb por release. in case of an under-voltage on any of the outputs or an over- temperature event, this pin is used to report the fault condition by being pulled to 5vsb. ss (pin 13) connect a small ceramic capacitor (allowable range: 5nf- 0.22 f; 0.1 f recommended) from this pin to gnd. the internal soft-start (ss) current source along with the external capacitor creates a vo ltage ramp used to control the ramp-up of the output voltages. pulling this pin low with an open-drain device shuts down all the outputs as well as 5vdual switch controller (v out3 ) 5vdl under-voltage rising threshold - 3.750 - v 5vdl under-voltage hysteresis - 260 - mv 5vdlsb output drive current i 5vdlsb 5vdlsb = 4v -20 - -40 ma 5vdlsb pull-up impedance to 5vsb - 350 - ? timing intervals active state assessment past 12v threshold note 2 40 50 60 ms maximum allowable s3 to s5 skew - 200 - s 5vsb por extension past threshold voltage -3.3- ms control i/o (s3 , s5 , en3vdl , en5vdl, fault) high level threshold --2.2v low level threshold 0.8 - - v s3 ,s5 internal pull-up impedance to 5vsb - 70 - k ? fault output impedance fault = high - 100 - ? fault under-voltage reporting delay -10- s temperature monitor fault-level threshold note 3 125 - - c shutdown-level threshold note 3 - 150 - c notes: 2. guaranteed by correlation. 3. guaranteed by design. electrical specifications recommended operating conditions, unless otherwise noted. refer to figures 1, 2 and 3 (continued) parameter symbol test conditions min typ max units HIP6501A
6 forces the fault pin low. the c ss capacitor is also used to provide a controlled voltage slew rate during active-to-sleep transitions on the 3.3v dual and 2.5/3.3v mem outputs. 12v (pin 14) connect this pin to the atx (or equivalent) 12v output. this pin is used to monitor the status of the power supply as well as provide bias for the nmos -compatible output drivers. 12v presence at the chip in th e absence of bias voltage, or severe 12v brownout during active states (s0, s1) operation can lead to chip misbehavior. vsen2 (pin 16) connect this pin to the memory output (v out2 ). in sleep states, this pin is regulated to 2.5v or 3.3v (based on r sel ) through an internal pass transistor capable of delivering 300ma (typically). when v out2 is programmed to 2.5v, the active-state voltage at this pin is regulated through an external npn transistor connected at the drv2 pin. for the 3.3v setting, the at x 3.3v is passed to this pin through a fully on n-mos transistor. duri ng all operating states, the voltage at this pin is monitored for under-voltage events. drv2 (pin 15) for the 2.5v rdram systems, co nnect this pin to the base of a suitable npn transistor. this pass transistor regulates the 2.5v output from the atx 3.3v during active states operation. for 3.3v sdram system s connect this pin to the gate of a suitable n-mos transistor ; this transistor is used to switch in the atx 3.3v output. 3v3dl (pin 4) connect this pin to the 3.3v dual output (v out1 ). in sleep states, the voltage at this pin is regulated to 3.3v; in active states, atx 3.3v output is delivered to this node through a fully on n-mos transistor. during all operating states, this pin is monitored for under-voltage events. 3v3dlsb (pin 3) connect this pin to the base of a suitable npn transistor. in sleep states, this transistor is used to regulate the voltage at the 3v3dl pin to 3.3v. dla (pin 10) connect this pin to the gates of suitable n-mosfets, which in active states, are used to switch in the atx 3.3v and 5v outputs into the 3.3v dual and 5v dual outputs, respectively. 5vdl (pin 12) connect this pin to the 5v dual output (v out3 ). in either operating state, the voltage at this pin is provided through a fully on mos transistor. this pin is also monitored for under- voltage events. 5vdlsb (pin 11) connect this pin to the gate of a suitable p-mosfet or bipolar pnp. in sleep states, this transistor is switched on, connecting the atx 5vsb output to the 5v dual regulator output. description operation the HIP6501A controls 3 output voltages (refer to figures 1, 2, and 3). it is designed for microprocessor computer applications with 3.3v, 5v, 5 vsb, and 12v outputs from an atx power supply. the ic is composed of two linear controllers supplying the pci slots? 3.3v aux power (3.3v dual , v out1 ) and the 2.5v rdram or 3.3v sdram memory power (2.5/3.3v mem , v out2 ), and a dual switch controller supplying the 5v dual voltage (v out3 ). in addition, all the control and monitoring functions necessary for complete acpi implementat ion are integrated into the HIP6501A. initialization the HIP6501A automatically initializes upon receipt of input power. the power-on reset (por) function continually monitors the 5vsb inpu t supply voltage, in itiating soft-start operation after it exceeds its por threshold (in either s3 or s4/s5 states). to ensure stabilization of the 5vsb supply before operation is allowed, por is released 3.3ms (typically) after 5vsb exceeds the por threshold. the 5vsb por trip event is also used to lock in the memory voltage setting based on r sel . operational truth tables the en3vdl and en5vdl pins offer a host of choices in terms of the overall system architecture and supported features. tables 1-3 descri be the truth combinations pertaining to each of the three outputs. as seen in table 1, en3vdl simply controls whether the 3.3vdual plane remains powered up during s4/s5 sleep state. table 1. 3.3v dual output (v out1 ) truth table en3vdl s5 s3 3v3dl comments 0 1 1 3.3v s0, s1 states (active) 0103.3vs3 0 0 1 note 4 maintains previous state 0003.3vs4/s5 1 1 1 3.3v s0, s1 states (active) 1103.3vs3 1 0 1 note 4 maintains previous state 1000vs4/s5 note: 4. combination not allowed. HIP6501A
7 very similarly, table 2 details the fact that en5vdl status controls whether the 5v dual plane supports sleep states. as seen in table 3, 2.5/3.3v mem output is maintained in s3 (suspend-to-ram), but not in s4/s5 state. the dual-voltage support accommodates both sdram as well as rdram type memories. additionally, the internal ci rcuitry does not allow the transition from an s3 (suspend to ram) state to an s4/s5 (suspend to disk/soft off) state or vice versa. the only ?legal? transitions are from an active state (s0, s1) to a sleep state (s3, s4/s5) and vice versa. functional timing diagrams figures 4-8 are timing diagrams, detailing the power up/down sequences of all three outputs in response to the status of the enable (en3vdl , en5vdl) and sleep-state pins (s3 , s5 ), as well as the status of the atx supply. the status of the en3vdl and en5vdl pins can only be changed while in active (s0, s1) states, when the bias supply (5vsb pin) is below por level, or during chip shutdown (ss pin shorted to g nd); a status change of these two pins while in a sleep state is ignored. not shown in these diagrams is the de-glitching feature used to protect against false sleep state tripping. once the status of the s3 pin changes, an internal time r is activated. if at the end of the timeout period (typically 200 s) the input pins present a valid state change r equest, then the controller transitions to the new configuration. otherwise, the previously attained valid state is maintained until valid control signals are received from the system. this particular feature is useful in noisy co mputer environments if the control signals have to travel over significant distances. table 2. 5v dual output (v out3 ) truth table en5vdl s5 s3 5vdl comments 0 1 1 5v s0, s1 states (active) 0100vs3 0 0 1 note 5 maintains previous state 0000vs4/s5 1 1 1 5v s0, s1 states (active) 1105vs3 1 0 1 note 5 maintains previous state 1005vs4/s5 note: 5. combination not allowed. table 3. 2.5/3.3v mem output (v out2 ) truth table r sel s5 s3 2.5/3.3v mem comments 1k ? 1 1 2.5v s0, s1 states (active) 1k ? 1 0 2.5v s3 1k ? 0 1 note 6 maintains previous state 1k ? 00 0vs4/s5 10k ? 1 1 3.3v s0, s1 states (active) 10k ? 1 0 3.3v s3 10k ? 0 1 note 6 maintains previous state 10k ? 00 0vs4/s5 note: 6. combination not allowed. figure 4. 3v dual and 5v dual timing diagram for en3vdl = 1, en5vdl = 1 figure 5. 3v dual and 5v dual timing diagram for en3vdl = 1, en5vdl = 0 5vsb 12v s3 s5 5vdlsb dla 3v3dlsb 3v3dl 5vdl 5vsb 12v s3 s5 5vdlsb dla 3v3dlsb 3v3dl 5vdl HIP6501A
8 soft-start circuit soft-start into sleep states (s3, s4/s5) the 5vsb por function initiates the soft-start sequence. an internal 10 a current source charges an external capacitor to 5v. the error amplifiers reference inputs are clamped to a level proportional to the ss (soft-start) pin voltage. as the ss pin voltage slews from about 1.25v to 2.5v, the input clamp allows a rapid and controlled output voltage rise. figure 9 shows the soft-start sequence for the typical application start-up in a sleep state with all output voltages enabled. at time t0 5v sb (bias) is applied to the circuit. at time t1, 5v sb surpasses por level, and an internal fast charge circuit quickly raises the ss capacitor voltage to approximately 1v. at this point, the 10 a current source continues the charging up to t2, where a voltage of 1.25v (typically) is reached and an internal clamp limits further charging. clamping of the soft-start voltage (t2 to t3 interval) should only be noticed with capacitors smaller than 0.1 f; soft-start capacitors of 0.1 f and above should present a soft-start ramp void of this plateau. at time t3, 3ms (typically) past the 5v sb por (t1), the memory output voltage selection is latched in and the charging of the soft- start capacitor resumes, using the 10 a current source. at this point, the error amplifiers? reference inputs are starting their transitions, causing the output voltages to ramp up proportionally. the ramping continues until time t4 when all the voltages reach the set value. at time t5, when the soft- start capacitor value reaches approximately 2.8v, the under- voltage monitoring circuits are activated and the soft-start capacitor is quickly discharged down to the value attained at time t2 (approximately 1.25v). figure 6. 3v dual and 5v dual timing diagram for en3vdl = 0, en5vdl = 1 figure 7. 3v dual and 5v dual timing diagram for en3vdl = 0, en5vdl = 0 figure 8. 2.5/3.3v mem timing diagram 5vsb 12v s3 s5 5vdlsb dla 3v3dlsb 3v3dl 5vdl 5vsb 12v s3 s5 5vdlsb dla 3v3dlsb 3v3dl 5vdl 5vsb 12v s3 s5 drv2 vsen2 vsen2 internal device figure 9. soft-start interval in a sleep state (all outputs enabled) 0v 0v time soft-start (1v/div) output (1v/div) voltages v out1 (3.3v dual ) v out2 (2.5v mem ) v out3 (5v dual ) t1 t2 t3 t0 5vsb (1v/div) uv detect enable (logic level) t5 t4 HIP6501A
9 soft-start into active states (s0, s1) if both s3 and s5 are logic high at the time the 5vsb is applied, the HIP6501A will assume an active state and keep off the controlled external transistors until about 50ms after the atx?s 12v output (sensed at the 12v pin) exceeds the set threshold (typically 10.8v). this timeout feature is necessary in order to ensure the main atx outputs are stabilized. the timeout also assures smooth transitions from sleep into active when sleep states are being supported. during sleep to active state transitions from conditions where the outputs are initially 0v (such as s4/s5 to s0 transition with en3vdl = 1 and en5vdl = 0, or simple power-up sequence directly into active state), the 3v dual and 5v dual outputs go through a quasi soft-start by being pulled high through the body diodes of the n-channel mosfets connected between these outputs and the 3.3v and 5v atx outputs, respectively. figure 10 shows this start- up scenario. 5v sb is already present when the main atx outputs are turned on at time t0. similarly, the soft-start capacitor has already been charged up to 1.25v and the clamp is active, awaiting for the 12v por timer to expire. as a result of 3.3v in and 5v in ramping up, the 3.3v dual and 5v dual output capacitors charge up through the body diodes of q3 and q5, respectively (see figure 3). at time t1, the 12v atx output exceeds the HIP6501A?s 12v under-voltage threshold, and the internal 50ms (t ypical) timer is initiated. at t2 the time-out initiates a so ft-start, and the memory output is ramped-up, reaching regulation limits at time t3. simultaneous with the memory voltage ramp-up, the dla pin is pulled high (to 12v), turning on q3 and q5, and bringing the 3.3v dual and 5v dual outputs in regulation at time t2. at time t4, when the soft-start voltage reaches approximately 2.8v, the under-vol tage monitoring circuits are enabled and the soft-start capacitor is quickly discharged to approximately 2.45v. requests to go into a sleep state during an active state soft- start ramp-up result in a chip reset, followed by a new soft- start sequence into the desired state. fault protection all the outputs are monitored against under-voltage events. a severe over-current caused by a failed load on any of the outputs, would, in turn, caus e that specific output to suddenly drop. if any of the out put voltages drop below 69% of their set value, such event is reported by having the fault/msel pin pulled to 5v. additionally, the 2.5/3.3v memory regulator is internally current limited while in a sleep state. exceeding the maximum cu rrent rating of this output in a sleep state can lead to output voltage drooping. if excessive, this droop can ultimately trip the under-voltage detector and send a fault signal to the computer system. however, a fault condition will only set off the fault flag, and it will not shut off or latch off any part of the circuit. if shutdown or latch off of the circuit is desired, this can be achieved by externally pulling or latching the ss pin low. pulling the ss pin low will also force the fault pin to go low. under-voltage sensing is disabled on all disabled outputs and during soft-start ramp-up intervals. ss voltage reaching the 2.8v threshold signals activation of the under-voltage monitor. another condition that could set off the fault flag is chip over-temperature. if the HIP6501A reaches an internal temperature of 125 o c (minimum), the fault flag is set (fault/msel pulled high), but the chip continues to operate until the temperature reaches 150 o c (typical), when unconditional latched shutdown of all outputs takes place. the thermal latch can be reset only by cycling the 5v sb off, and then on. output voltages the output voltages are internally set and do not require any external components. selection of the memory voltage is done by means of an external resistor connected between the fault/msel pin and ground. an internal 40 a (typical) current source creates a voltage drop across this resistor. during every 5vsb trip above po r level, this voltage is compared with an internal reference (200mv typically). based on this comparison, the ou tput voltage is set at either 2.5v (r sel = 1k ? ), or 3.3v (r sel = 10k ? ). it is very important that no capacitor is connected to the fault/msel pin; the presence of a capacitive element at this pin can lead to false memory voltage selection. see figure 11 for details. figure 10. soft-start interval in an active state 0v 0v time soft-start (1v/div) output (1v/div) voltages t1 t2 t0 input voltages (2v/div) t4 t3 +5v in +12v in dla pin +5vsb v out2 (2.5v mem ) v out1 (3.3v dual ) v out3 (5v dual ) (2v/div) +3.3v in HIP6501A
10 application guidelines soft-start interval the 5vsb output of a typical atx supply is capable of 725ma. during power-up in a sleep state, it needs to provide sufficient current to charge up all the output capacitors and simultaneously provide some amo unt of current to the output loads. drawing excessive amounts of current from the 5vsb output of the atx can lead to voltage collapse and induce a pattern of consecutive restarts with unknown effects on the system?s behavior or health. the built-in soft-start circuitry allows tight control of the slew- up speed of the output voltages controlled by the HIP6501A, thus enabling power-ups free of supply drop-off events. since the outputs are ramped up in a linear fashion, the current dedicated to charging the output capacitors can be calculated with the following formula: , where i ss - soft-start current (typically 10 a) c ss - soft-start capacitor v bg - bandgap voltage (typically 1.26v) ( c out xv out ) - sum of the products between the capacitance and the voltage of an output. due to the various system timing events, it is recommended that the soft-start interval not be set to exceed 30ms. additionally, the recommended soft-start capacitor range spans from 5nf up to 0.22 f (0.1 f recommended). shutdown in case of a fault condition that might endanger the computer system, or at any othe r time, the HIP6501A can be shut down by pulling the ss pin below the specified shutdown level (typically 0.8v) with an open drain or open collector device capable of sinking a minimum of 2ma. pulling the ss pin low effectively shuts down all the pass elements. upon release of the ss pin, the HIP6501A undergoes a new soft-start cycle and resumes normal operation in accordance to the atx supply and control pins status. layout considerations the typical application employ ing a HIP6501A is a fairly straight-forward implementation. similar to any other linear regulators, attention has to be paid to a few potentially sensitive small signal components, such as those connected to high-impedance nodes or those supplying critical by-pass currents. the power components (pass transistors) and the controller ic should be placed first. the controller should be placed in a central position on the motherboard, closer to the memory load if possible. ensure t he vsen2 connecti on is properly sized to carry 200ma without si gnificant resist ive losses. the pass transistors should be placed on pads capable of heatsinking, matching the device?s power dissipation. where applicable, multiple via connections to a large internal plane can significantly lower localized device temperature rise. placement of the decoupling and bulk capacitors should follow a placement reflecting their purpose. as such, the high-frequency decoupling capacitors (c hf ) should be placed as close as possible to the load they are decoupling; the ones decoupling the controller (c 12v , c 5vsb ) close to the controller pins, the ones de coupling the load close to the load connector or the load itself (if embedded). the bulk - + figure 11. 2.5/3.3v mem output voltage selection circuitry details fault/msel 40 a mem voltage select comp r sel r sel v mem 1k ? 10k ? 2.5v 3.3v + - 0.2v i cout i ss c ss v bg -------------------------------- c out v out () = figure 12. printed circuit board islands v out1 q1 q2 q3 q4 c ss +12v in c in via connection to ground plane island on power plane layer island on circuit/power plane layer c bulk2 HIP6501A c 12v v out2 v out3 ss gnd vsen2 5vdlsb drv2 3v3dlsb key 12v 5vsb +5v sb dla q5 c bulk1 c bulk3 c 5vsb load c hf1 c hf3 5vdl +5v in c hf2 +3.3v in 3v3dl load load HIP6501A
11 capacitance (aluminum electrolyt ics or tantalum capacitors) placement is not as critical as the high-frequency capacitor placement, but having these capacitors close to the load they serve is preferable. the only critical small signal component is the soft-start capacitor, c ss . locate this component close to ss pin of the control ic and connect to ground through a via placed close to the capacitor?s ground pad. minimize any leakage current paths from ss node, since the internal current source is only 10 a. a multi-layer printed circuit board is recommended. figure 12 shows the connections of most of the components in the converter. note that the individual capacitors each could represent numerous physical capacitors. dedicate one solid layer for a ground plane and make all critical component ground connections through vias placed as close to the component as possible. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. ideally, the power plane should support both the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers to create power islands connecti ng the filtering components (output capacitors) and the load s. use the remaining printed circuit layers for small signal wiring. component selection guidelines output capacitors selection the output capacitors for all outputs should be selected to allow the output voltage to meet the dynamic regulation requirements of active state operation (s0, s1). the load transient for the various microprocessor system?s components may require high quality capacitors to supply the high slew rate (di/dt) current demands. thus, it is recommended that capacitors c out1 and c out2 should be selected for transient load regulation. also, during the transition between active and sleep states, there is a short interval of time during which none of the power pass elements are conducting - during this time the output capacitors have to supp ly all the output current. the output voltage drop during this brief period of time can be approximated with the following formula: , where ? v out - output voltage drop esr out - output capacitor bank esr i out - output current during transition c out - output capacitor bank capacitance t t - active-to-sleep or sleep-t o-active transition time (10 s typical) since the output voltage drop is heavily dependent on the esr (equivalent series resistance) of the output capacitor bank, the capacitors should be chosen to maintain the output voltage above the lowest allowable regulation level. input capacitors selection the input capacitors for an HIP6501A application must have sufficiently low esr so that the input voltage does not dip excessively when energy is transferred to the output capacitors. if the atx supply does not meet the specifications, certain imbalances between the atx?s outputs and the HIP6501A?s regulation levels could result in a brisk transfer of energy from the input capacitors to the supplied outputs. when transiting from active to sleep states, this phenomena could result in the 5vsb voltage dropping below the por level (typically 4.3v) and temporarily disabling the HIP6501A. the solution to this potential problem is to use lar ger input capacitors (on 5vsb) with a lower total combined esr. transistor select ion/considerations the HIP6501A typically requires one p-channel and two n-channel power mosfets and two bipolar npn transistors. one general requirement for selection of transistors for all the linear regulators/switchin g elements is package selection for efficient removal of heat. the power dissipated in a linear regulator/switching element is: select a package and heatsink that maintains the junction temperature below the rating with the maximum expected ambient temperature. q1 the active element on the 2.5v/3.3v mem output has different requirements for each of the two voltage settings. in 2.5v systems utilizing rdram (or voltage-compatible) memory, q1 must be a bipolar npn capable of conducting the maximum required output current and it must have a minimum current gain (h fe ) of 100-150 at this current and 0.7v v ce . in such systems, the 2.5v output is regulated from the atx 3.3v output while in an active state. in 3.3v systems (sdram or compatible) q1 must be an n-channel mosfet, since the mosfet serves as a switch during active states (s0, s1). the main criteria for the selection of this transistor is output voltage budgeting. the maximum r ds(on) allowed at highest junction temperature can be expressed with the following equation: , where v in min - minimum input voltage v out min - minimum output voltage allowed i out max - maximum output current the gate bias available for th is mosfet is approximately 8v. ? v out i out esr out t t c out ----------------- - + ?? ?? ?? = p linear i o v in v out ? () = r ds on () max v in min v outmin ? i out max ------------------------------------------------------------ = HIP6501A
12 q4 if a p-channel mosfet is used to switch the 5vsb output of the atx supply into the 5v dual output during s3 and s4/s5 states (as dictated by en5vdl status), then, similar to the situation where q1 is a mosfet, the selection criteria of this device is also proper voltage budgeting. the maximum r ds(on) , however, has to be achieved with only 4.5v of v gs , so a logic level mosfet needs to be selected. if a pnp device is chosen to perform this function, it has to have a low saturation voltage while providing the maximum sleep-state current and have a current gain sufficiently high to be saturated using the minimum dr ive current (typically 20ma; 4ma during soft-start). q3, q5 the two n-channel mosfets are used to switch the 3.3v and 5v inputs provided by the atx supply into the 3.3vdual and 5vdual outputs, respectively, while in active (s0, s1) states. similar r ds(on) criteria apply in these cases as well, unlike the pmos, however, these nmos transistors get the benefit of an increased v gs drive (approximately 8v and 7v, respectively). q2 the npn transistor used as sleep-state pass element on the 3.3v dual output must have a minimum current gain of 100 at v ce = 1.5v, and i ce = 500ma throughout the in-circuit operating temperature range. HIP6501A
13 HIP6501A applic ation circuit figure 13 shows an application circuit of an acpi-compliant power management system for a microprocessor computer system. the power supply provides the pci 3.3v dual voltage (v out1 ), the rdram 2.5v mem memory voltage (v out2 ), and the 5v dual voltage (v out3 ) from +3.3v, +5v, +5vsb, and +12vdc atx supply outputs. for systems employing sdram memory, replace r1 with 10k ? and q1 with an huf76113sk8. q4 can also be a pnp, such as an mmbt2907al. for detailed information on the circuit, including a bill-of-materials and circuit board description, see application note an9846. see intersil?s web site www.intersil.com for the latest information. c6 c5 r1 2x150 f 1 f 150 f 220 f gnd 5vsb +3.3v in +5v sb vsen2 drv2 s3 c8,9 HIP6501A 12v +12v in v out2 2.5v mem q1 s3 s5 s5 v out1 3.3v dual +5v in c11 v out3 5v dual 3v3dl 3v3dlsb q2 q3 q4 dla 5vdlsb fault/msel 5vdl ss en5vdl en5vdl en3vdl en3vdl + + c4 1 f c2 1 f c3 220 f + c10 1 f + 1k 1 f c12 1 f 2sd1802 2sd1802 fdv304p shutdown 1/2 huf76113dk8 c7 u1 c13 0.1 f (from open-drain n-mos) c1 10 f figure 13. typical HIP6501A application circuit q5 1/2 huf76113dk8 + HIP6501A
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HIP6501A small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - b 0.014 0.019 0.35 0.49 9 c 0.007 0.010 0.19 0.25 - d 0.386 0.394 9.80 10.00 3 e 0.150 0.157 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 1 02/02

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